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Effect of traps in the performance of four gate transistors

  • A. Luque Rodriguez
  • , J. A.Jimenez Tejada
  • , A. Godoy
  • , J. A.López Villanueva
  • , F. M. Gómez-Campos
  • , S. Rodríguez-Bolivar

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

In this work, a study of traps located in the bulk and the Si-SiO 2 interfaces of four gate transistors (G4-FETs), and their effect in the performance of these transistors, is presented. Different kinds of low frequency noise spectra measured at different voltages applied to the gates show that traps in the bulk and traps at the interfaces are the origin of such different spectra. We propose a model to evaluate low frequency noise produced in the bulk and surfaces of the device. This model is incorporated in a 2D simulator that confirms the experimental trends. It also allows us to separate the contribution of both sources and study the effects of different kinds of bulk traps on the low frequency noise.

Original languageEnglish
Title of host publicationProceedings of the 2009 Spanish Conference on Electron Devices, CDE'09
Pages132-135
Number of pages4
DOIs
StatePublished - 24 Apr 2009
Externally publishedYes
Event2009 Spanish Conference on Electron Devices, CDE'09 - Santiago de Compostela, Spain
Duration: 11 Feb 200913 Feb 2009

Publication series

NameProceedings of the 2009 Spanish Conference on Electron Devices, CDE'09

Conference

Conference2009 Spanish Conference on Electron Devices, CDE'09
Country/TerritorySpain
CitySantiago de Compostela
Period11/02/0913/02/09

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