Effect of traps in the performance of four gate transistors

  • A. Luque Rodriguez
  • , J. A.Jimenez Tejada
  • , A. Godoy
  • , J. A.López Villanueva
  • , F. M. Gómez-Campos
  • , S. Rodríguez-Bolivar

Producción científica: Capítulo del libro/informe/acta de congresoContribución a la conferenciarevisión exhaustiva

3 Citas (Scopus)

Resumen

In this work, a study of traps located in the bulk and the Si-SiO 2 interfaces of four gate transistors (G4-FETs), and their effect in the performance of these transistors, is presented. Different kinds of low frequency noise spectra measured at different voltages applied to the gates show that traps in the bulk and traps at the interfaces are the origin of such different spectra. We propose a model to evaluate low frequency noise produced in the bulk and surfaces of the device. This model is incorporated in a 2D simulator that confirms the experimental trends. It also allows us to separate the contribution of both sources and study the effects of different kinds of bulk traps on the low frequency noise.

Idioma originalInglés
Título de la publicación alojadaProceedings of the 2009 Spanish Conference on Electron Devices, CDE'09
Páginas132-135
Número de páginas4
DOI
EstadoPublicada - 24 abr. 2009
Publicado de forma externa
Evento2009 Spanish Conference on Electron Devices, CDE'09 - Santiago de Compostela, Espana
Duración: 11 feb. 200913 feb. 2009

Serie de la publicación

NombreProceedings of the 2009 Spanish Conference on Electron Devices, CDE'09

Conferencia

Conferencia2009 Spanish Conference on Electron Devices, CDE'09
País/TerritorioEspana
CiudadSantiago de Compostela
Período11/02/0913/02/09

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